The present disclosure relates to stabilization methods for making polymer dielectric that is useful in the manufacturing of future integrated circuits (“IC's”). The present disclosure relates to, in particular, stabilization methods for making a polymer film to achieve its best electrical performance after film deposition. In addition, it relates to post treatment methods to retain the chemical integrity on film surface during and after exposure to chemical processes, especially after reactive plasma etching of the dielectric that employed during the fabrication of IC's. The post treatment method will assure good adhesion and film integrity to a subsequent top layer film.
During the manufacturing of IC's, multiple layers of films are deposited. Maintaining the compatibility and structural integrity of the different layers throughout the processes involved in finishing the IC is of vital importance. In addition to dielectric and conducting layers, its “barrier layer” may include metals such as Ti, Ta, W, and Co and their nitrides and silicides, such as TiN, TaN, TaSixNy, TiSixNy, WNx, CoNx and CoSiNx. Ta is currently the most useful barrier layer material for the fabrication of future IC's that use copper as conductor. The “cap layer or etch stop layer” normally consists of dielectric materials such as SiC, SiN, SiON, silicon oxide (“SiyOx”), fluorinated silicon oxide (“FSG”), SiCOH, and SiCH.
The schematic in FIG. 1 is used to illustrate some fundamental processes involved for fabrication of a single Damascene structure and future IC's. During fabrication of future ICs, first a dielectric 110 is deposited on wafer using a Spin-On or Chemical Vapor Deposition (“CVD”) dielectric. Then, a photoresist is spun onto the substrate and patterned using a photo mask and UV irradiation. After removal of unexposed photoresist and form a pattern of cured photoresist over the underlying dielectric, a via in the dielectric layer is formed by plasma etching of the dielectric that is not protected by the photoresist. Then, a thin layer (100 to 200 Å) of barrier metal 130 such as Ta is deposited using physical vapor deposition (“PVD”) method. This is followed by deposition of a very thin (50 to 100 Å) layer of copper seed 150 using PVD or Metal-Organic CVD (“MOCVD”). After that, the via is filled with copper 140 by ECP (“Electro-Chemical Plating”) method. After the copper is deposited, Chemical Mechanical Polishing (“CMP”) may be needed to level the surface of the Damascene structure. Optionally, a cap-layer is deposited over the dielectric before coating of photoresist and photolithographic pattering of the dielectric. The cap-layer can be used to protect the dielectric from mechanical damage during CMP.
In our U.S. Pat. No. 6,825,303, transport polymerization (“TP”) methods and processes for making low dielectric polymers that consist of sp2C—X and HC-sp3Cα—X bonds were revealed. Wherein, X is H or preferably F for achieving better thermal stability and lower dielectric constant of the resulting polymers. HC-sp3Cα—X is designated for a hyper-conjugated sp3C—X bond or for a single bond of X to a carbon atom that is bonded directly to an aromatic moiety. Due to hyper-conjugation (see p. 275, T. A. Geissman, “Principles of Organic Chemistry,” 3rd edition, W. H. Freeman & Company), this C—X (X═H or F) has some double-double bond character, thus they are thermally stable for fabrications of future ICs.
However, we have observed that after transport polymerization, an as-deposited thin film may not achieve its best dimensional and chemical stability. Therefore, in the U.S. Pat. No. 6,703,462, deposition conditions and post treatment methods to achieve high dimensional stability from the as-deposited films are described.
In this application, methods to optimize the chemical stability thus achieving best electrical performance for an as-deposited film are described. In addition, after reactive plasma etching of a dimensionally and chemically stabilized film, the surface chemical composition of the resulting film has changed. Due to degradation of surface composition under reactive conditions, loss of adhesion between dielectric film and barrier metal, cap layer or etch-stop layer can occur. Therefore, processing conditions are disclosed to provide good chemical stability thus interfacial adhesion between the dielectric film and the subsequently deposited top layer such as the barrier metal, the cap layer or etch-stop layer.